The present invention relates generally to semiconductor logic devices, such as memory chips, data registers and the like. More particularly, the present invention relates to such devices having data output pins which connect to input signals having voltages below common (e.g., 0 volts).
Semiconductor logic devices, which include a wide variety of types and applications, employ logic circuitry to manipulate or store input data and an output buffer to provide the manipulated or stored data at an output terminal of the device. Depending on the type of logic device and/or the circuit environment in which the device is used, the output buffer""s output terminal can be connected to one or more input signals which provide a negative voltage level, often as low as xe2x88x921 volt. For example, the output terminal (or xe2x80x9cdata terminalxe2x80x9d) of a memory device, such as a DRAM, is typically used to receive input signals as well as to provide output signals. output buffer is disabled so that it does not provide a voltage bias to the input signal at the data terminal. Similarly, the output terminal of a latch, although not necessarily having a xe2x80x9creceivexe2x80x9dmode, is typically connected to a signal-receiving data bus, and the output terminal of the latch is controlled, so as not to provide a voltage bias to the bus.
In either situation, when the output terminal is connected to an input signal which provides a negative voltage level as low as, e.g., xe2x88x921 volt, certain transistors in the output buffer can be activated. For instance, the portion of the output buffer which provides the high-level logic signals at the terminal is typically coupled to transistors which are activated in response to such a negative voltage level being presented at the output terminal. The activated transistors can cause excessive substrate current to flow and excessive drain current to pass to ground (or common) through this portion of the output buffer (sometimes referred to as xe2x80x9cpull-upxe2x80x9d circuitry). This results in wasted current and, in some instances, causes the output buffer to latch-up and therefore fail.
One known approach for mitigating this problem is to implement the pull-up circuitry using two transistor devices in series rather than one transistor by itself. Because the drain-source voltage across each of the two devices is reduced, the conduction of current is reduced by the same factor. A disadvantage in this approach, however, is that by doubling the number of transistors in series, the device widths must also be doubled in order to get the same drivexe2x80x94that requires four times as much current to drive these devices but still results in the same output current and four times as much space. Moreover, to accommodate the same level of current drive through the series-arranged transistors, the width requirement for manufacturing each transistor is effectively doubled, which represents a four-fold increase in terms of semiconductor space. Further, control circuits, including large capacitors, are often used in this arrangement to drive the series-arranged transistors, and this requires more space and impairs the speed of the output buffer. Thus, this approach is burdensome in terms of space, speed, and current consumption.
Another approach is to implement the pull-up circuitry using one pull-up device, but with an additional transistor device and resistor arranged to bias the input (or gate) of the pull-up device to a low-level voltage in response to such a negative voltage level being presented at the output terminal. This approach reduces the gate-source voltage across the pull-up device and thereby slightly reduces the substrate current and slightly reduces the consumption of drain current during this condition. Unfortunately, the extent of current reduction is relatively insubstantial. In addition, the pull-up device is still active when the negative voltage level is present at the output terminal, and this causes excess current to be drawn from other devices through the output terminal.
The above-mentioned problems are believed to have been discovered in connection with the conception and implementation of the present invention, which provides a number of features and advantages, including solutions to these problems.
Generally, the present invention provides an improved semiconductor output buffer arrangement for overcoming the previously-discussed deficiencies of the prior art. For instance, when used with N-channel pull-up transistors arranged to drive output terminals (or xe2x80x9cpinsxe2x80x9d when the terminals connect to external leads of a chip), the present invention provides an output buffer arrangement which reduces the flow of substrate current by reducing the gate-to-source and drain-to-source voltages of the pull-up transistors when the associated output pins connect to input signals having voltages below common.
In one embodiment, the present invention provides a semiconductor chip, comprising a logic circuit generating a control signal and an output circuit which is responsive to the control signal. The output circuit includes an output terminal, a high-level circuit having an input arranged to bias the output terminal toward a high-level voltage, a low-level circuit for biasing the output terminal toward a low-level voltage, and a disable circuit coupled to the input of the high-level circuit and responsive to a low-level signal at the output terminal, the low-level signal having a voltage less than the low-level voltage. The disable circuit responds to the low-level signal by causing the current through the high-level circuit to be interrupted.
In another embodiment, the present invention provides a tri-state output buffer for use in a semiconductor circuit device. The output circuit, which is responsive to a control signal generated in the semiconductor circuit device, comprises a power supply signal providing at least one voltage level with respect to common, an output terminal, a pull-up node, a pull-down node, a first circuit responding to the control signal by providing a first control voltage on the pull-up node, and a second circuit responding to the control signal by providing a second control voltage on the pull-down node. Further, a pull-up transistor responds to the voltage on the pull-up node and is coupled between the power supply signal and the output terminal, and a pull-down transistor responds to the voltage on the pull-down node and is coupled between common and the output terminal. A bias circuit, responsive to a voltage level on the output terminal being at a level substantially below common, is constructed and arranged to bias the pull-up node downwardly and away from the voltage level provided by the power supply signal. A disable circuit, responsive to the voltage level on the output terminal being at a level substantially below common, is constructed and arranged to disable the circuit providing the control voltage on the pull-up node. The pull-up transistor provides a high-level signal at the output terminal, the pull-down transistor provides a low-level signal at the output terminal, and the bias and disable circuits respond to the voltage level on the output terminal being at a level substantially below common by preventing current flow from the power supply signal to the output terminal.
The above summary of the present invention is not intended to present each embodiment or every aspect of the present invention. This is the purpose of the figures and the associated description which follow.